By Johan Huijsing, Michiel Steyaert, Arthur H.M. van Roermund
This 10th quantity of "Analog Circuit layout" concentrates on three issues: Scalable Analog Circuits, High-Speed D/A Converters, and RF strength Amplifiers. each one subject is roofed via 6 papers, written by way of overseas famous specialists on that subject. those papers have an academic nature geared toward enhancing the layout of analog circuits. The ebook is split into 3 elements: half I, Scalable Analog Circuit layout describes in 6 papers problems with: scalable high-speed layout, scalable high-resolution mixed-mode ADC and OpAmp layout, scalable high-voltage layout for XDSL, scalability of wire-line entrance ends, reusable IP analog layout, and porting CAD analog layout. half II, High-Speed D/A Converters describes in 6 papers problems with: creation to high-speed D/A converter layout, retargetable 12-bit 200-MHz CMOS present guidance layout, high-speed CMOS D/A converters for upstream cable functions, static and dynamic functionality barriers, the linearity problem of D/A converters for communications, and a 400-MHz, 10-bit charge-domain CMOS D/A converter for low-spurious frequency synthesis. half III, RF strength Amplifiers describes in 6 papers problems with: process points, assessment and trade-offs, linear transmitter architectures, GaAs microwave SSPAs, Monolithic transformer-coupling in Si-bipolar, and RF strength amplifier layout in CMOS. "Analog Circuit layout" is a necessary reference resource for analog layout engineers and researchers wishing to maintain abreast with the most recent advancements within the box. the educational insurance additionally makes it appropriate to be used in an develop layout direction.
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Additional info for Analog Circuit Design: Scalable Analog Circuit Design
5 (unpublished) essentially splits the signal by frequency into three paths which are recombined by summing the 36 outputs of transconductance stages, with the lowest frequencies passing through a chopped or auto-zeroed path with 5 gain stages while the high frequencies have a short un-chopped 2-stage path. This design only works well over a limited input CM range as the input differential pairs require some voltage headroom and if used in a noninverting configuration the harmonic distortion will be limited by the input pair common mode rejection ratio.
Approaches have been proven often feasible and on a case-by-case basis economically applicable to address different applications and market segments; both approaches have been also adopted in case of XDSL. Common to both th e two approaches is the requirement for high-speed components showing high ft and minimum parasitic capacitances even when withstanding high voltage condition. To better understand the implication involved in realizing such a kind of components it is worth referring, for sake of simplicity, to the voltage limitations of npn transistor.
We assume this is very familiar. However, it is badly effected by all the scaling issues summarised above. The following discussion assumes an objective of a scalable opamp architecture suited to buffering A/D and D/A converters with >12 bits resolution over a signal bandwidth from DC to several MHz. g. 5 inverter stages suppression of low frequency flicker noise (which of course also brings good DC performance). Rail-to-rail output stage design is well known  and the textbook methods appear adequately scalable with stacking of threshold and saturation voltages which can be accommodated within the shrinking supplies.