Integrating Functional and Temporal Domains in Logic Design: by Patrick C. McGeer

By Patrick C. McGeer

This ebook is an extension of 1 author's doctoral thesis at the fake direction challenge. The paintings used to be started with the belief of systematizing a few of the options to the fake course challenge that were proposed within the literature, which will picking the computational rate of every as opposed to the achieve in accuracy. even though, it grew to become transparent that many of the proposed ways within the literature have been fallacious in that they lower than­ expected the serious hold up of a few circuits below moderate stipulations. extra, another methods have been obscure and so of questionable accu­ racy. the point of interest of the study consequently shifted to developing a idea (the viability thought) and algorithms that could be assured right, after which utilizing this thought to justify (or now not) current ways. Our quest used to be profitable sufficient to justify offering the entire information in a e-book. After it used to be came upon that a few current methods have been improper, it grew to become obvious that the basis of the problems lay within the makes an attempt to stability computational potency and accuracy by means of setting apart the pace­ ral and logical (or sensible) behaviour of combinational circuits. This separation is the fruit of a number of unspoken assumptions; first, that it is easy to forget about the logical relationships of wires in a community while contemplating timing behaviour, and, moment, that you could forget about timing concerns whilst trying to realize the values of wires in a circuit.

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Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications

This publication is an extension of 1 author's doctoral thesis at the fake course challenge. The paintings was once started with the belief of systematizing many of the suggestions to the fake course challenge that have been proposed within the literature, for you to making a choice on the computational rate of every as opposed to the achieve in accuracy.

Extra resources for Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications

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For i = 0, we have eo is a change in a primary input and this clearly occurs at t = 0 = w(fo). Assume for i :5 j. For j + 1, we have that ej+1 occurs as a direct consequence of ej, whence 0+1 t(ej+1) = t(ej) + w(fj+t> , hence t(ej+1) = ~i=o w(fi). 1 A path {fo, ... iL (Cl' C2, Ti-l) = 1. ~ Proof: ~ {fo, ... , 1m} is sensitizable. 1 we have that event ei occurs at Ti occurring as a result of the event at Ti-l on Ii-I. -1 is satisfied (so that Ii-I going low forces Ii low). , at Ti-I. This is summarized in the expression: The other case is that Ii (q, C2, Tj) tracks Ii-I (q , C2, Tj_ t>, in which case we must have that Ii /;-1 is satisfied (so that Ii-I going low forces Ii high), and that Ii'i_l is satisfied (so that Ii-I going high forces Ii low).

We do so by induction on the maximum distance (in nodes, not node weights) of a node n from the primary inputs, denoted 6(n), and called the level of n. Note for every node m in the transitive famn of n, we have that 6(n) > 6(m), and that the only nodes p for which 6(P) = 0 are the primary inputs. Hence inductive proofs on 6(m) are really proofs on the structure of a graph; we will be showing that, given that a property holds for each node in the transitive famn of some node, then it holds at that node.

Under this criterion, a path is false if there exists no input condition such that all gates along the path are sensitized to the value of the previous gate on the path. This approach has recently been formalized in the SLOCOP timing environment[6]. Unfortunately, not every true path is statically sensitizable, so the delay of the longest statically sensitizable path is not necessarily an upper bound on the delay of the circuit. In this chapter we demonstrate that 29 2. THE FALSE PATH PROBLEM 30 the use of static sensitization as a criterion for the truth or falsity of a path can lead to underestimates of circuit delay, possibly causing the circuit to behave incorrectly.

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