NAND Flash Memory Technologies by Seiichi Aritome

By Seiichi Aritome

  • Offers a finished assessment of NAND flash stories, with insights into NAND heritage, know-how, demanding situations, evolutions, and perspectives
  • Describes new application disturb matters, facts retention, strength intake, and attainable ideas for the demanding situations of 3D NAND flash memory
  • Written through an expert in NAND flash reminiscence expertise, with over 25 years’ experience

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A detailed program and an erase operation are described in the following. The program operation of a NAND flash cell is performed by applying highvoltage Vpgm to control gate (CG) while keeping substrate/source/drain 0 V, as shown in Fig. 10. Electrons are injected to the floating gate (FG) by a Fowler–Nordheim (FN) tunneling mechanism through the tunnel oxide. Vt of cell has a positive shift. An erase operation is performed by applying high-voltage Vera to substrate (p-well), while keeping CG at 0 V.

Are possible by combination of these ways of injection and ejection, as shown in Fig. 9. The first one is the NOR-type flash program/erase scheme. CHE injection is used for programming, and source FN ejection is used for erase. The second one is the new NOR-type flash program/erase scheme [7]. CHE injection is used for programming, and channel FN ejection is used for erase. The third one is the old program/erase scheme for NAND flash [8, 9]. Drain FN ejection is used for programming, and channel FN injection is used for erasing.

A 4-Mbit NAND-EEPROM with tight programmed Vt distribution, VLSI Circuits, 1990. Digest of Technical Papers, 1990 Symposium on, pp. 105–106, 7–9 June 1990. ; Masuoka, F. A 4 Mb NAND EEPROM with tight programmed Vt distribution, Solid-State Circuits, IEEE Journal of, vol. 26, no. 4, pp. 492–496, Apr. 1991. ; Masuoka, F. A NAND structured cell with a new programming technology for highly reliable 5 V-only flash EEPROM, 1990 Symposium on VLSI Technology, 1990. Digest of Technical Papers, pages 129–130, 1990.

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