Trace-based post-silicon validation for VLSI circuits by Xiao Liu

By Xiao Liu

This publication first offers a entire insurance of state of the art validation ideas in accordance with real-time sign tracing to assure the correctness of VLSI circuits. The authors talk about numerous key demanding situations in post-silicon validation and supply automatic ideas which are systematic and cost effective. a sequence of computerized tracing suggestions and leading edge layout for debug (DfD) suggestions are defined, together with concepts for hint sign choice for boosting visibility of useful error, a multiplexed sign tracing procedure for making improvements to practical mistakes detection, a tracing resolution for debugging electric mistakes, an interconnection cloth for expanding information bandwidth and aiding multi-core debug, an interconnection cloth layout and optimization strategy to raise move flexibility and a DfD layout and linked tracing resolution for making improvements to debug potency and increasing tracing window. The suggestions awarded during this publication enhance the validation caliber of VLSI circuits, and finally permit the layout and fabrication of trustworthy digital devices.

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One method is to run simulation with operational input 36 4 Multiplexed Tracing for Design Error sequence and then dump internal values to estimate it. 5 to be value 0/1. With these notations, after the evidence passes through a gate, it is weakened as E Iout = E Iin × W P. Re-convergent fan-out may cause multiple propagated evidences to propagate through the same gate. To capture this effect, we introduce E Iin evi. × W Pnon−evi. , within which the W Pnon−evi. is the expression E Iout = determined by the inputs without propagated evidences.

3 Proposed Methodology The design flow of the proposed multiplexed signal tracing method is described in Fig. 4. , interconnection fabric and debug controller as shown in Fig. 1) are inserted in the design (detailed in Sect. 1). Then, during the post-silicon debug phase, for a particular suspicious region relevant to one or more trigger conditions, we use an off-chip algorithm to determine signal grouping for maximizing error detection capability in that region (detailed in Sect. 2). The arrangement is loaded into on-chip debug controller through JTAG interface to facilitate multiplexed trace control.

1 depicts a conceptual hardware infrastructure for trace-based debug techniques. As signal tracing involves non-trivial DfD overhead, only a small portion of “key” signals in the circuit are tapped, and in each debug run, a subset of the tapped signals are traced concurrently. An interconnection fabric is used to link the large number of tapped signals to the trace buffers/ports. The trigger unit controls the start Design Phase Erroneous RTL Fabrication Test Input Vector Erroneous Circuit Specification High Level Simulation Violate Dumped State Value Conflict Debug Phase Fig.

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