VLSI Design for Video Coding: H.264/AVC Encoding from by Youn-Long Steve Lin, Chao-Yang Kao, Hung-Chih Kuo, Jian-Wen

By Youn-Long Steve Lin, Chao-Yang Kao, Hung-Chih Kuo, Jian-Wen Chen

Back conceal Copy

VLSI layout for Video Coding

By:

Youn-Long Lin

Chao-Yang Kao

Jian-Wen Chen

Hung-Chih Kuo

High definition video calls for large compression on the way to be transmitted or saved economically. Advances in video coding criteria from MPEG-1, MPEG-2, MPEG-4 to H.264/AVC have supplied ever expanding coding potency, on the price of serious computational complexity which could basically be brought via vastly parallel processing.

This e-book provides VLSI architectural layout and chip implementation for top definition H.264/AVC video encoding with an entire FPGA prototype. It serves as a useful reference for a person drawn to VLSI layout for video coding.

• offers cutting-edge VLSI architectural layout and chip implementation for prime definition H.264/AVC video encoding;

• Employs vastly parallel processing to bring 1080pHD, with effective layout that may be prototyped through FPGA;

• each subsystem is gifted from usual specification, algorithmic description, layout issues, timing making plans, block diagram to test-bench verification;

Show description

Read or Download VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip PDF

Best cad books

Computer-Aided Design, Engineering, & Manufacturing Systems Techniques & Applications, The Design of

Within the aggressive enterprise enviornment businesses needs to continuously try to create new and higher items quicker, extra successfully, and extra affordably than their rivals to achieve and retain the aggressive virtue. Computer-aided layout (CAD), computer-aided engineering (CAE), and computer-aided production (CAM) are actually the typical.

Mastering Revit Structure 2009

The contents of the booklet are sturdy and it ia a superb place to begin to get accostumed to the Revit constitution atmosphere. I want the scale of the letters have been a section larger and that the e-book had a spouse CD or web site to entry a few uncomplicated pattern records to accomplish tutorials and excercise different suggestions of the software program.

VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip

Again conceal CopyVLSI layout for Video CodingBy:Youn-Long LinChao-Yang KaoJian-Wen ChenHung-Chih KuoHigh definition video calls for enormous compression that allows you to be transmitted or kept economically. Advances in video coding criteria from MPEG-1, MPEG-2, MPEG-4 to H. 264/AVC have supplied ever expanding coding potency, on the rate of significant computational complexity which may in simple terms be added via hugely parallel processing.

Integrating Functional and Temporal Domains in Logic Design: The False Path Problem and Its Implications

This booklet is an extension of 1 author's doctoral thesis at the fake direction challenge. The paintings used to be all started with the assumption of systematizing a number of the ideas to the fake direction challenge that were proposed within the literature, to be able to deciding upon the computational rate of every as opposed to the achieve in accuracy.

Additional info for VLSI Design for Video Coding: H.264/AVC Encoding from Standard Specification to Chip

Example text

On the other hand, the Level D 44 3 Integer Motion Estimation a b N + SRH –1 N + SRV –1 N + SRV –1 N-1 N 1 c SRH –1 d N 1 N-1 1 W + SRH –1 SRV –1 CB 1 CB 2 N N + SRV –1 N N 1 N + SRH –1 Fig. SRV 1/ scheme achieves the lowest off-chip memory traffic but has the largest size local memory. Presently, most ME designs adopt the Level C scheme to strike a balance between memory size and traffic. 3 A VLSI Design for Integer Motion Estimation We propose a multiple(P)-macroblock data-reuse scheme in Sect.

The widths of A0 , B0 , . . , and G1 are all 16 pixels. 23a shows the data flow when two reference frames are processed sequentially. In Step 1, PE-arrays 1–4 perform block matching of CB1 against A0 . In Step 2, B0 is broadcasted to PE-arrays 1–4 and PE-arrays 5–8 for block matching of CB1 and CB2 , respectively. After Step 4, block matching of CB1 against RF0 is completed. In Step 5, block matching of CB1 against RF1 starts and A1 is transferred to PE-arrays 1–4. However, block matching of CB2 CB4 is still in RF0 and E0 is broadcasted to PE-arrays 5–8, 9–12, and 13–16.

Consequently, there are totally (2SRV =N ) (2SRV =N ) sets of PEs for the whole search window. By twodirectional data broadcasting, this design further increases data-reuse ratio. Komarek and Pirsch [34] proposed a 2D array architecture as shown in Fig. 9. Each current pixel is stored in a PE and hence the number of PEs is equal to the current block size (block size N D 4 in Fig. 9). Instead of broadcasting, reference 0 1 D D PE 0 PE 1 D PE 2 PE 14 Comparator MV Fig. 7 Yang’s 1D array architecture D PE 15 38 3 Integer Motion Estimation Current Reference Pixel Pixel0 PE PE PE PE Reference Pixel1 D D D D PE PE PE PE D D D D PE PE PE PE D D D D PE PE PE PE D D D Comparator MV Fig.

Download PDF sample

Rated 4.61 of 5 – based on 13 votes
Posted in Cad